As integration levels of integrated circuits expand, semiconductor chip size has continuously increased, and accordingly, each chip may contain a plurality of macros. These macros may be of similar functionality, such as memory arrays (i.e., DRAMs), or of differing functionality, such as mixed digital and analog macros. The production yield of these chips can be greatly improved if extra, or redundant, macros are prepared.
An article entitled “256-Mb DRAM Circuit Technologies for File Applications” in the IEEE Journal of Solid State Circuits, vol. 28, no. 11, November 1993, pp. 1105–1113, discusses the effect that chip integration has had on chip yield. FIG. 1 is a chart taken from the article showing the ratio of these different faults for each generation of DRAM technology. As shown in FIG. 1, the trend indicates as the integration level has progressed, the fatal fault and excessive stand-by current fault (Isb fault) over-dominates the traditional bit and line fault.
To improve chip yield, several redundancy schemes have been employed to overcome the Isb fault. One such scheme is to remove a power supply to a defective macro on the chip. For example, one can design a power switch for each macro, so when the macro is found to be defective, the power switch is turned off and the supply power to the macro is cut-off. However, this scheme requires a large area of the integrated circuit chip to form a low impedance switch. Additionally, when the switch is large, it is vulnerable and subject to off-state leakage. On the other hand, if the switch is not properly sized, the impedance could hurt the circuit performance.
The above-mentioned article suggests a sub-array replacement redundancy scheme, as shown in FIG. 2, employing a power switch and fuse ROM. In this scheme, all sub-arrays of a macro are tested one by one concerning DC current. The fuse ROMs are used to store the test results and control the switches. The power switches of the defective sub-arrays are turned off and the power switches for the good spare sub-arrays are turned on.
Another well-known prior art scheme is to use “header” and “footer” devices to selectively switch on and off a portion of a circuit, i.e., a defective macro. Similar to the power switch scheme, this approach is not area efficient. Besides, it consumes energy to switch on and off the huge header and footer devices.
Another approach is to provide an array of laser, or electrical, fuses between an external power supply and the macro power supply system. An array of fuses is needed in order to avoid high impedance occurrences in the power supply. When a macro must be disabled, the whole array of fuses is blown using conventional blowing techniques. Due to the ablative nature of fuse blowing techniques, this scheme is not a clean process. For example, sometimes, the remaining debris could form an unwanted high resistive path, especially when blowing a full array of fuses located in close proximity to each other. Unlike signal fuse blowing, this scheme is not a fully reliable method. Besides, this is a non-reversible process, once the macro is blown, it cannot be reconnected to the power supply.